I was studying Instruction cycle from "Computer System Architecture" by Morris Mano .Under timing and control topic,fetching cycle is explained like this:
T0: AR<--PC
T1:IR<--M[AR],PC<--PC+1
IR-Instruction Register
AR-Address Register
PC-Program Counter
However, according to my understanding of previous topics PC can be incremented with T0 control signal.Please explain is it possible?/