Timing Diagram. HELP PLEASE!

[blindislands]

Hello I have two questions about timing diagram but I have no idea how to do them, and the due date is like 2 days away. Please help me. Thank you.

1) The circuit shown here needs to have its timing checked for specific input sequences on A, B and C.
Complete the timing diagram shown for this circuit. All gates have 1 unit delay.

2)Inputs A and B have the sequence shown. Draw the full waveform responses for Q and QB. Each
gate has a 1 unit delay. In the sample timing chart shown the vertical lines represent that one time
unit.

[blindislands]

This is what I got for f. A straigh line with output 1 at all time... It seems to be odd

[Mouche]

I know the due date has already passed, but I'll give you some advice anyway.

The best way to determine the entire output signal for a circuit is to split it up in chunks where the inputs change.

For example, ignoring the exact timing, here is the sequence of inputs you have for question 1:

A B C
1 0 0
0 0 0
0 0 1
0 1 1
1 1 0
0 0 0

For each of these inputs, look at the circuit and find what f should be. For the first line, the output of the OR gate is 1, the output of the AND gate is 0, and then the output of the NAND gate is 1. So, f = 1.

Let's say those dotted lines are 10 ns and the gate delay is 10 ns. Since the inputs propagate through 2 gates to get to f, the total gate delay is 20 ns. That means you draw the f value you calculated 2 dotted lines after the inputs change. The actual answer is likely different since I pulled random values out of the air.