Member Avatar for Rohan_12

Hello Everyone,
I have an FPGA application that has some function (i.e: Matrix Multiplication) now I want to create the memory interface for FPGA communication based on the model pushed into the FPGA?
For example, If we have the size of 1024 and the size of data is 10 bit how we can create memory interface a/c to the actual size?

  1. What are the possibilities which can achieve this mechanism?

  2. Can you help me to make pseudo-code or c-code?

    I am trying to used sds_lib.h (same as #include ) functions but I have no idea how to that programitically , I tried by my self but still don't know am I doing right or wrong. I have read about memory mapped I/O region but still not clear to me.

I would really appreciate if someone could help me.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/sdsoc_doc/topics/api/reference_sdsoc_api.html

Thanks,

RS

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  • Latest Post Latest Post by rproffitt
Member Avatar for rproffitt

This is the missing piece of information that could explain your prior post about C++ to C. I can see where a Xilinx system that only offered C could have a new engineer going down that rabbit hole.

It's been well over a decade since I worked with Xilinx, Atmel and other devices but for this level of support you should be getting with your Xilinx Field Engineer. Or going with a design or consulting firm to get your product off the ground.

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