Member Avatar for Rohan_12

Hello Everyone,
I have an FPGA application that has some function (i.e: Matrix Multiplication) now I want to create the memory interface for FPGA communication based on the model pushed into the FPGA?
For example, If we have the size of 1024 and the size of data is 10 bit how we can create memory interface a/c to the actual size?

  1. What are the possibilities which can achieve this mechanism?

  2. Can you help me to make pseudo-code or c-code?

    I am trying to used sds_lib.h (same as #include ) functions but I have no idea how to that programitically , I tried by my self but still don't know am I doing right or wrong. I have read about memory mapped I/O region but still not clear to me.

I would really appreciate if someone could help me.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/sdsoc_doc/topics/api/reference_sdsoc_api.html

Thanks,

RS

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  • Latest Post Latest Post by rproffitt

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A short, practical recipe for (and a note for — the Xilinx field engineer route is sensible for a product, but the steps below let an engineer prototype and validate the interface).

Start by picking the memory domain that fits the model size. 1024×10 bits is small enough to live in on‑chip BRAM/URAM for a fully‑local accelerator, or in off‑chip DDR for larger datasets or streaming. For a PS↔PL flow the common pattern is: control registers over AXI‑Lite, bulk data over AXI‑Stream or AXI‑DMA/AXI‑MM (AXI DMA supports wide data buses, scatter/gather and alignment options). ()

Practical steps (works for SDSoC / Vitis flow):

  • Pack the 10‑bit samples into a bus‑friendly word size (example below packs three 10‑bit values into one 32‑bit word). Packing simplifies the PL IP and the AXI data alignment.
  • Allocate a physically‑contiguous DMA buffer from SDSoC so the PL/DMA engine can read it directly (use SDSoC allocation APIs when compiling with sdscc). (studylib.net)
  • Before launching DMA, flush or mark the CPU cache appropriately; after DMA completes, invalidate the cache range so the CPU sees PL‑written data. On Xilinx platforms the BSP APIs for data cache flush/invalidate are used for this step. (studylib.net)
  • Use the AXI DMA driver/example code supplied with the tools to submit transfers and handle completion/interrupts. Example drivers show the cache synchronization pattern used in real projects. (xilinx.github.io)

Example packing pseudocode (adapt for your build):

#include <stdint.h>
#include <stdlib.h>
#ifdef __SDSCC__
#include <stdlib.h>
#include "sds_lib.h"
#define my_alloc(s) sds_alloc(s)
#define my_free(p)  sds_free(p)
#else
#define my_alloc(s) malloc(s)
#define my_free(p)  free(p)
#endif

// pack 10-bit samples (0..1023) into 32-bit words (3 samples per word)
void pack10_to_u32(const uint16_t *in, uint32_t *out, size_t n) {
    size_t i=0, j=0;
    while (i + 2 < n) {
        out[j++] = (in[i] & 0x3FF)
                 | ((in[i+1] & 0x3FF) << 10)
                 | ((in[i+2] & 0x3FF) << 20);
        i += 3;
    }
    if (i < n) { // leftover
        uint32_t w = 0; int sh = 0;
        while (i < n) { w |= (in[i++] & 0x3FF) << (sh); sh += 10; }
        out[j++] = w;
    }
}

Troubleshooting notes and cautions:

  • Make buffers aligned to the DMA and cache‑line boundaries (check platform cache alignment). If running Linux prefer the kernel coherent APIs (dma_alloc_coherent / dmasync*), otherwise use SDSoC's physically‑contiguous alloc or non‑cacheable allocation and explicit cache syncs. (kernel.org)
  • Start simple: transfer a short known pattern, loopback, or ping‑pong buffers and verify with the PL ILA or logic probe before scaling up.
  • If time/quality constraints exist, involve a Xilinx field engineer or an experienced consultant for production deployment (AXI/DDR timing, cache coherence and driver corner cases are common pitfalls).

This gives a straightforward mapping from 1024×10‑bit data to a DMA/AXI friendly layout, how to allocate and sync buffers in SDSoC/Vitis, and the tests to validate the path.

Member Avatar for rproffitt

This is the missing piece of information that could explain your prior post about C++ to C. I can see where a Xilinx system that only offered C could have a new engineer going down that rabbit hole.

It's been well over a decade since I worked with Xilinx, Atmel and other devices but for this level of support you should be getting with your Xilinx Field Engineer. Or going with a design or consulting firm to get your product off the ground.

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