Member Avatar for evios

hi there,
i was currently given a task as shown above....
however what i had was juz a small program code (in assembly) between the two..
i need something longer where i can further look into its pipelining,
becoz i still need to analyze each of the instruction cycle...
Thanks for those can help.

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  • Latest Post Latest Post by Duoas
Member Avatar for Duoas

Since no one has answered this...

In a normal branch, the branch test is performed and the next opcode fetched depends on the result of the test. It might be the next opcode or it might be the opcode at the address indicated by the branch.

The net result is that the next opcode to actually be executed is not fetched until after the branch test is performed. This breaks the rhythm of the processer's fetch-execute loop, meaning that time is wasted.

A delayed branch tries to speed things up by fetching (and sometimes executing) a certain number of opcodes following the branch opcode regardless of the test result.

For simple tests this can speed things up a little, and when working with assembly instructions every little bit counts.

In order to avoid nasty side-effects, the assembler will typically insert a requisite number of no-ops after the branch opcode.

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