Member Avatar for wsn

Hi,

I'm trying to make a makefile but after i enter the command
make makefile
it says nothing to be made in the makefile, can someone please help me?
Nd.c depends on Pd.h
Pd.c depends on Pd.h
Md.c depends on md.h
md.h depends on Rd.h

# Makefile

CC = gcc
LD = $(CC)
DEPEND = mkdep

CFLAGS = -O2 -Wall

CFILES =\
Nd.c\
Pd.c\
Md.c

HFILES =\
md.h\
Pd.h\
Rd.h

OFILES = $(CFILES:%.c=%.o)

myprogram: $(OFILES)
$(LD) -o $@ $(OFILES)

Nd.o: Nd.c Pd.h

Pd.o: Pd.c Pd.h

Md.o: Md.c md.h

md.h: Rd.h

depend:
$(DEPEND) $(CFLAGS) $(CFILES)

clean:
rm -f *.o *.bak

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Member Avatar for jephthah

why are you trying to make your makefile?

the command should just be "make"... should it not?

Member Avatar for wsn

Thank you that really helped i didn't know i was running the command wrong
but still my makefile isn't working i tried to simplify it more but the last two dependencies aren't working

myprogram: Nd.o Pd.o Md.c
gcc Nde.o Pd.o Md.o -o myprogram
Nd.o:
gcc -c Nd.c
Pd.o:
gcc -c Pd.c
Md.o: Md.c md.h
gcc -c Md.c
md.h: Rd.h

Member Avatar for jephthah

are you using <TAB> in front of each command? i cant tell since youre not using code-tags.

dont "simplify" it until you get it to work in the first place. go back to the beginning and adhere strictly to your dependency graph

________   ________   ________
| ND.C |   | PD.C |   | MD.C |
========   ========   ========  
    |____  ____|          |
        |  |              |
      __V__V__        ____V___
      | PD.H |        | MD.H |
      ========        ========
                          |
                      ____V___
                      | RD.H |
                      ========
Edited by mike_2000_17 because: Fixed formatting
commented: Very helpful gave me a very good hint where I was lost thank you +3
Member Avatar for wsn

solved it thank u very much

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