Member Avatar for Allasso

Hello,

Is there a reference anywhere that I can find out the number of cycles each instruction takes for ia-32 processors?

I do not find this information in the docs, neither has much googling come up with anything.

Thanks,

Allasso

Edited by Allasso because: n/a
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The short answer is that "cycles per instruction" for IA‑32 is not a single, stable table: numbers change with microarchitecture (P5/P6, NetBurst, Core, Atom, etc.), front‑end/decoder behavior, micro‑ops, and whether an instruction is measured as latency (dependent chain) or reciprocal throughput (sustained rate). asked for a reference and pointed to community tables — those are useful starting points, but the reliable approach is to combine vendor docs with targeted measurement on the exact CPU being used.

A practical measurement recipe (keep everything measured on the target CPU):

  1. Isolate the test: pin the process to one core and set a steady power governor if possible.
  2. Use a serializing read of the timestamp counter (common pattern: serialize; read TSC; run test; read TSC; serialize) so timing brackets are not reordered.
  3. Measure latency with a dependent chain (each instruction uses the previous result).
  4. Measure throughput with many independent instructions (different registers) to saturate execution ports.
  5. Run many iterations, warm caches, subtract loop overhead, and average.
  6. Cross‑check with hardware performance counters or a profiler to confirm retire counts and stall reasons.

Authoritative references to consult by name: Intel Software Developer Manuals and the Intel Optimization Reference; independent, measured tables (community-maintained instruction tables and uop/latency databases) are very helpful for comparing microarchitectures. Use profilers (Linux perf, Intel VTune, etc.) and small microbenchmarks rather than trusting a single published number.

Cautions: results are affected by CPU frequency scaling, Turbo/Power management, SMT/Hyperthreading, branch mispredicts, cache/TLB misses, instruction fusion, and alignment. For real optimizations, measure the actual hot loop on the target machine and focus on whether latency or throughput is the dominant limiter for that loop.

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Member Avatar for Tight_Coder_Ex

Here is instruction set with clocks

Keep in mind, in a multithreaded operating system, cycles are only realative as other concurrent processes are using CPU at same time, which will affect the throughput of application of interest.

Member Avatar for Allasso

perfect, thanks.

regarding your comment, I am assuming however, that it is still best to choose the combination of instructions that result in the fewest clocks (as if the program were the only thread) within a given program, no?

Member Avatar for Allasso

...it would be nice to find this on the pentiums as well. And all the rest out there...

Member Avatar for Tight_Coder_Ex

Definately, as that is what I try to do with my apps, espcially those with high interation loops. I found that link pretty easy, so maybe do your query more like a question that keywords.

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